? 2010 device engineering incorporated page 1 of 6 ds-mw-01044-02 rev. f 11/12/10 features: ? converts arinc 429 levels to ttl/cmos digital data. ? meets requirements of arinc 429 digital information transfer system standards. ? inputs internally protected to lightnin g requirements of do-160d level a3. ? operates at data rates beyond ar inc 429 specifications to 5mhz. ? 5 volt or 3.3 volt operation. ? 20l 4.4mm tssop package. ? one-half volt receiver hysteresis. ? operates within 5 volts common mode input voltage range. ? bicmos process ? DEI1044 has ttl/cmos test inputs functional description: the DEI1044 and dei1045 are quad arinc 429 line receiver ics implemented in bicmos technology. they contain four differential line receivers. each receiver channel translates in coming arinc 429 data bus signals to a pair of ttl/cmos outpu ts. each receiver operates independently, is lightning protected, and meets a ll requirements of the arinc 429 digital information transfer standard . the DEI1044 ic includes two test inputs for built in system tes t. they force the outputs of all receivers to the specified zero , one or null state. the arinc inputs are ignored when the devic e is in test mode. the dei 1045 does not have test inputs. the DEI1044/1045 quad line receiver can be used in conjunction with device engineering?s family of avionics products in interfacing the arinc 429 data bus. table 1 function table test a test b in n a - in n b out n a out n b l l one +10v h l l l zero -10v l h l l null 0v l l l h x l h h l x h l h h x l l test inputs are internally set to l on dei1045 DEI1044, dei1045 quad arinc 429 line receiver device engineering incorporated 385 east alamo drive chandler, az 85225 phone: (480) 303-0822 fax: (480) 303-0824 e-mail: admin@deiaz.com figure 1: function diagram in n b resistor network and lightning protection output and test logic in n a comparators out n a out n b testa* testb* to other channels lightning protection notes: 1) one of four identical channels shown (n = 1 to 4) 2) * test inputs are no connect on dei1045
? 2010 device engineering incorporated page 2 of 6 ds-mw-01044-02 rev. f 11/12/10 pinout figure 2: 20l tssop pinout note: * pins 5 and 6 are ?no connect? on dei1045 electrical characteristics table 3: recommended operating conditions parameter symbol conditions supply voltage vdd +5v 10% +3.3v 10% logic input levels (DEI1044) v testa,b 0 to vcc operating temperature -tms top -55 to +85c -55 to +125c table 2: absolute maximum ratings parameter min max units supply voltage (vdd) -0.3 7.0 v storage temperature -65 +150 c input voltage (arinc input s) dc conditions. -30 +30 v input voltage (test inputs) v ss ? 0.3 v cc +0.3 v power dissipation @ 85 c 350 mw peak body temperature, - g package 260 c lightning protection (arinc 429 chan nel inputs and testa/testb inputs) waveform 3 (2) waveform 4 and 5 (2) -600 -300 +600 +300 v v notes: 1. stresses above these limits c an cause permanent damage. 2. per do160d, sect 22 level 3a. see figures 7-9. 3. the DEI1044 contains circuitry to protect inputs against damage due to high voltage static discharge. it has been characterized per jedec a114-a human body model to level 1 (1kv io immunity). observe precautions for handling and storing electrostatic sensitive devices. 7 6 5 4 3 2 1 14 15 16 17 18 19 20 in1 a 13 8 in1 b in2 a in2 b v dd gnd in3 a in3 b out3 a testb * testa * out2 b out2 a out1 b out1 a 12 11 9 10 in4 a in4 b out3 b out4 a out4 b
? 2010 device engineering incorporated page 3 of 6 ds-mw-01044-02 rev. f 11/12/10 table 4: electrical characteristics conditions: temperature: -55c to +85c (std versions), -55c to +125c (-tms versions) v dd = +5v 10% or 3.3v 10% parameter test condition symbol min nom max units arinc inputs v a ? v b out a = 1 v hi 6.5 10 13 v v a ? v b out b = 1 v lo -6.5 -10 -13 v v a ? v b out a = 0 out b = 0 v null -2.5 0 2.5 v input resistance in a to in b v dd open, shorted to v ss or +5v (1) r in 24k ? input resistance in a or in b to v ss v dd open, shorted to v ss or +5v r s 12k ? input hysteresis 0.5 1.0 v input capacitance in a to in b v dd open, shorted to v ss or +5v (1) c in 50 pf input capacitance in a or in b to v ss v dd open, shorted to v ss or +5v (1) c s 50 pf input common mode voltage v hi, v lo, v null at nominal values v cm -5 +5 v test inputs (DEI1044 only) logic 0 voltage v il 0.8 v logic 1 voltage v ih 2.0 v logic 0 current v il = 0.8 i il 1 a logic 1 current v ih = 2.0 i ih 20 a outputs out a or out b i oh = 5ma, v dd = 5v (1) i oh = 1.5ma, v dd = 3.3v v oh 2.4 v out a or out b i ol = 5ma, v dd = 5v (1) i ol = 1.5ma, v dd = 3.3v v ol 0.4 v out a or out b i oh = 100a (1) cmos compatible v oh v dd ? 50mv v out a or out b i ol = 100a (1) cmos compatible v ol v ss + 50mv v supply current v dd current a/b in open, a/b out open i dd 5.5 11 ma switching characteristics (1) max 3.3v max 5v prop delayin a/b to out a/b testa = testb = 0 t lh 95 55 ns prop delayin a/b to out a/b testa = testb = 0 t hl 70 45 ns out a/b rise time 10% to 90% t r 50 35 ns out a/b fall time 10% to 90% t f 25 15 ns testa/b to out a/b prop delay t toh 90 50 ns testa/b to out a/b prop delay t tol 90 50 ns n otes 1. guaranteed by design, not production tested. 2. current flowing into device is positive. current flowing out of device is negative. all voltages are with respect to ground unless otherwise noted.
? 2010 device engineering incorporated page 4 of 6 ds-mw-01044-02 rev. f 11/12/10 5a: 5b: t 0 50% peak t1 t2 v/i 0 t v/i 25% to 75% of largest peak 50% largest peak t 0 50% peak t1 t2 v figure 8: do160c/d voltage waveform #4 v oc = 300v, i sc = 60a figure 9: do160c/d voltage waveform #5 v oc = 300v, i sc = 300a t1 = 6.4 microseconds 20% t2 = 70 microseconds 20% t1 = 50 microseconds 20% t2 = 500 microseconds 20% notes: 1. v oc = peak open circuit voltage available at the calibration point. 2. i sc = peak short circuit current available at the calibration point. 3. amplitude tolerances: +10%, -0% 4. the ratio of v oc to i sc is the generator source impedance to be used for generator calibration purposes. figure 7: do160c/d voltage waveform #3 v oc = 600v, i sc = 24a, frequency = 1.0mhz 20% t1 = 40 microseconds 20% t2 = 120 microseconds 20% figure 3: input/output timing in a in b out a out b v a - v b = 6.5v t lh t hl 1.5v v a - v b = -6.5v t hl t lh 1.5v t toh t tol 1.5v 1.5v testa or b outa or b figure 4: test propagation delay 50pf outa or outb figure 5: output load t r t f 10% 90% outa or b figure 6: rise/fall time
? 2010 device engineering incorporated page 5 of 6 ds-mw-01044-02 rev. f 11/12/10 package description: figure 10: 20l tssop package dimensions
? 2010 device engineering incorporated page 6 of 6 ds-mw-01044-02 rev. f 11/12/10 table 5: package characteristics table package type 20l tssop, green reference 20l tssop g thermal resistance: ja (4 layer pcb with power planes) 90 c/w jc 17 c/w jedec moisture sensitivity level (msl) msl 1 / 260 c lead finish material / jedec pb-free code nipdau e4 pb-free designation rohs compliant jedec reference mo-153-ac table 6: screening process screening methods electrical test: room temperature 100% high temperature 100% @ +85 or 125 c low temperature 0.65% aql@ -55c table 7: ordering information dei part number marking (1) package temperature range test inputs DEI1044-g DEI1044 e4 20l tssop g -55 / +85 c yes DEI1044-tms-g DEI1044m e4 20l tssop g -55 / +125 c yes dei1045-g dei1045 e4 20l tssop g -55 / +85 c no dei1045-tms-g dei1045m e4 20l tssop g -55 / +125 c no notes: 1. all packages marked with lot code and date code. ?e4? after date code denotes pb free category. dei reserves the right to make changes to an y products or specifications herein. dei makes no warranty, representation, or gua rantee regarding suitability of its products for any particular purpose.
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